–of length with target within ±5 %
–nets with target impedance
–mm without reference plane
Impedance analysis in three steps. Each step refines the one before; the colours on the board show the latest result.
Accuracy
Impedance. Formulas (Hammerstad-Jensen, Wheeler, Wadell, IPC-2141): microstrip within 1–2 %, coupled and coplanar lines 5–15 % off (asymmetric stripline +11 %). Field solver: js_2d_fields by Henrik Forstén (GPL-3.0), quasi-static, included unmodified (revision ): within 1.7 % of the HFSS/Ansys references in his test suite, εeff within 1 %.
Deviation on ThunderScope cross-sections; reference is Forstén's own microstrip/stripline solver:
| Formula | Field solver |
| Microstrip 213 µm, with solder mask | +1.4 % | 0.0 % |
| Diff-Microstrip LVDS (127/130 µm) | +7.8 % | −0.3 % |
| Diff-Microstrip PCIe (191/127 µm) | +5.6 % | −0.3 % |
| Stripline In3, spacings 1:8 | +10.3 % | 0.0 % |
| Microstrip over 3 mm cut-out (HFSS) | +17 % | −0.5 % |
Lines and vias. RLGC within 2 % of HFSS; copper roughness presets are estimates. Vias as a physics-based ladder (return vias, antipads, stubs, back-drilling, pairs), compared with 3D results of kisi's FDTD solver: via impedance in the TDR median 1.4 %, 90th percentile 7.4 %; pairs within 3.5° phase; stub notch within 3 %.
Channel. Parasitics of series parts and packages are estimates (data/components.json). The eye uses the profile's linear transmitter and receiver: no IBIS models, equalisation, jitter or noise. The channel behind a connector is what you give in the interface's card: a lossy line or a Touchstone file.
Still open: validation against other solvers and against measurements (a test board is planned). Treat the numbers as plausible estimates, not as verified results.